Field of the Invention
The present invention relates to digital memory devices, and more particularly to NAND flash memory having physical attributes, read command clocking characteristics, and/or read output characteristics compatible with high performance serial NOR flash memory.
Description of Related Art
Serial NOR flash memory has become a popular alternative to conventional parallel NOR flash memory. Serial NOR flash memories offer several advantages including; lower pin-count, smaller packages, simpler printed circuit boards, lower power, comparable performance and reduced device and system-level costs. Today, serial NOR flash memories are offered in densities from 512 Kilobit to 1 Gigabit, and employ the popular Serial Peripheral Interface (“SPI”).
Single-bit SPI uses four pins for transferring commands, address and data to, and data from, the serial flash memory, namely: Chip Select (/CS), Clock (CLK), Data In (DI) and Data Out (DO). Multi-bit SPI which includes Dual SPI, Quad SPI and Quad Peripheral Interface (“QPI”) use the same four pins but reconfigurable to transfer more serial data per clock cycle. Dual SPI changes the DI and DO pins to bi-directional DIO (Input/Output) pins. Quad SPI also changes the DI and DO pins to DIO pins, and adds two additional DIO pins for a total of four DIO pins, for a total of six pins when /CS and CLK are considered. QPI has four DIO pins like Quad SPI, but allows for full quad (four DIO) operation even for initial commands. These multi-bit SPI variants, combined with increasing clock speeds, allow Serial NOR Flash to be used for fast code shadowing to Random Access Memory (“RAM”); see, e.g., U.S. Pat. No. 7,558,900 issued Jul. 7, 2009 to Jigour et al.
Code shadowing tends to be performed in the following manner. During system boot-up, all or a portion of the non-volatile data is transferred from the serial NOR flash into system random access memory (“RAM”). Code shadowing may also be done dynamically after system boot, where a smaller RAM may be time-shared as needed by dynamically shadowing portions of the larger serial NOR flash memory.
Since system boot-up time is directly related to how fast the code can be shadowed, the higher the performance of the serial NOR flash, the faster the system can boot. Typically, a single SPI read command is issued with a starting address, and then data is continuously clocked out until all needed code is transfer to RAM. Today's serial NOR flash memory can achieve continuous read transfer rates in excess of 50 megabytes/second when using the quad SPI interface at 104 MHz. Applications like digital TVs, set-top boxes, personal computers, DVD players, networking equipment and automotive displays are examples of applications that benefit from code shadowing with high speed serial NOR flash memory. Application specific controllers commonly design basic serial NOR flash SPI read commands into the hardware circuitry (“hardcoded”) so that upon power-up, all or a portion of the data can be quickly loaded into RAM for operation. The 03 hex Read command, for example, is typically hardcoded.
At densities of 256 Megabits and higher, the cost of serial NOR flash memory approaches and exceeds the cost of single level cell (“SLC”) NAND flash memory in densities of 512 Megabits and higher. The cost versus density advantage of SLC NAND flash memory is largely due to the inherently smaller memory cell size used in SLC NAND flash technology, which makes the cost to manufacture highly dense NAND flash memory much lower than NOR flash memory. Unfortunately, commonly used SLC NAND flash memory has architectural, performance and bad block limitations that make it difficult to support the high speed code shadow applications for which serial NOR flash memory is well suited.
Serial NOR flash memory allows data to be clocked out of the device from a specified starting address (such as address 0) in a continuous and sequential fashion, without any delay time between clocks or any need to wait and check whether the device is ready or busy. In contrast, NAND flash memory has relatively long access times per page, typically tRD=25 uS for a 2048+64 byte page. Once the page has been accessed, the data is clocked out sequentially and quickly, typically 25 nS per byte, but then another tRD is incurred for the next page access. Some NAND flash memory provide a cache read feature that allows the next page to be accessed while data from the previous page is being clock out. However, this operation still uses a Ready/Busy check to confirm that the NAND flash memory is ready to proceed, which results in slower code shadow performance.
While today's NAND flash memory can ideally achieve read transfer rates of 25 to 35 megabytes/second, this does not take into account time for handling error correction code (“ECC”) processing and bad block management. These activities can further reduce the transfer rate by half, and result in performance significantly lower than serial NOR flash memory.
NAND flash memory allows for a certain percentage, typically 2%, of the blocks (typically 64 pages per block, 128 kilobytes+4 kilobytes) to be bad and not usable for the application. Typically, these bad blocks can be located anywhere in the memory array, and so are tagged so that they can be identified and not used. Some NAND flash memories guarantee only the first block to be good. As a result, standard sequential and continuous code shadowing is unreliable since the next block accessed may be bad. In contrast, serial NOR flash memory offers 100% good memory cells over the entire addressable memory range.
The data integrity of NOR flash memory is also better than NAND flash memory. In fact, external application ECC software or internal on-chip ECC circuitry is typically used with SLC NAND flash memory to locate and correct single bit, or in some cases, multi-bit errors. While NAND flash memory with on-chip ECC tend to perform faster than external ECC, undesirable delays of up to 100 uS per page read must be taken into consideration.
Serial NOR flash memory is available with the 4 to 6 active pin SPI interface and in small space efficient packages such as the 8-contact WSON, the 24-ball BGA, and the 8-pin and 16-pin SOIC. In contrast, ordinary parallel NAND flash memory typically employs 14 to 22 active pins housed in a relatively large 48-pin TSOP or 63-Ball BGA package that consumes up to twice the printed circuit board space of a serial NOR flash memory; see, for example, SK Hynix Inc., I Gbit (128M×8 bit/64M×16 bit) NAND Flash Memory, Rev. 1.1, November 2005; Micron Technology, Inc., 1 Gb NAND Flash Memory, Rev. E, 2006. Ordinary serial NAND flash memory have been introduced with the SPI interface; see, for example, Micron Technology, Inc., Get More for Less in Your Embedded Designs with Serial NAND Flash, Jul. 28, 2009, but such ordinary serial NAND flash memory tends to be housed in larger packages such as the 63-ball BGA, and have the same architectural, performance and bad block limitations that ordinary NAND flash memory has. Additionally these serial NAND flash memories do not offer command compatibility with the serial NOR flash memories on the market; see, e.g., Winbond Electronics Corporation, W25Q64CV SpiFlash 3V 64M-Bit Serial Flash Memory with Dual and Quad SPI, Revision F, May 7, 2012; Winbond Electronics Corporation, W25Q128FV SpiFlash 3V 128M-Bit Serial Flash Memory with Dual/Quad SPI & QPI, Revision D, Oct. 1, 2012.